DDR, Pcie, Debugging, Ethernet, Sata, Soc Architecture, ASIC design flow, Synthesis, ARM cores, RTL Coding, Timing Closure, DMA, Verification

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

Verification methodology., IP design verification, Functional coverage, systemverilog, LINT, ARM SoCs, Rtl Design

2d graphics , Verilog, C++ Programming, Opengl, Directx, Gpu, RTL, 3D Graphics, systemverilog, Rtl Design