ASIC RTL Design Engineer, Silicon

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

Cache, Soc Architecture, Perl, Verilog, Python, power analysis, Synthesis, memory compression, FPGA design verification, systemverilog, digital logic design principles, logic synthesis techniques, RTL design concepts, Dft, FPGA and emulation platforms, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

RTL design (SystemVerilog), Scripting (Python/Perl), Low power estimation, Debugging functional/performance simulations, ARM-based SoCs

2d graphics , Verilog, C++ Programming, Opengl, Directx, Gpu, RTL, 3D Graphics, systemverilog, Rtl Design