ASIC Engineer, IP Design

Responsibilities

• Work as part of the team that delivers coherent fabric interconnect solutions.
• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.

Minimum qualifications:

• Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience.
• 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture.
• 5 years of experience with ARM-based System on a Chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology.
• Experience with a coding language like Python or Perl.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
• 6 years of industry experience with Intellectual Property (IP) design.
• Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC).
• Experience with methodologies for low power estimation, timing closure, synthesis.