C, Vcs, Perl, Verilog, cdc, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, Veloce, formal verification

Scripting (Python/Perl), Rtl Design, Low power estimation, Timing Closure, Microarchitecture, systemverilog

Vcs, Verilog, Gdb, ASIC design flow, Rtl Design, floor-planning, Eco, Timing Analysis, Debussy, bring-up lab debug

Perl, Verilog, Python, Tcl, quartus, VHDL, Vivado, FPGA IP Design Validation, Vlsi Design, systemverilog

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, systemverilog, Rtl Design, spyglass, EVE, Veloce, formal verification

Hard IP integration, Clock and Power distribution, STA setup convergence methodology, Power Integrity Analysis, Hierarchical design implementation, Automation scripts within STA tools, Timing Closure, Timing ECO Implementation, Floor Planning, Debugging skills in implementation issues, ASIC Physical implementation, Global signal planning, Physical convergence, Tweaker Primetime based ECO flows

Networking Protocols, spyglass, Verilog RTL coding, Verplex LEC, high-speed serial interfaces, Synopsys Design Compiler, ASIC Design, multi-domain clock synchronization, high performance memory subsystems, ASIC debugging