- Lead the Power-On Reset validation of Processor and ASIC chips. Define and develop the validation strategy, plan and required infrastructure.
- You will be part of the design team which will deliver this critical infrastructure to IBM's Mainframe, POWER processors, and other ASICs.
- Lead the bringup & validation of POR boot engine and other related subsystems. Prepare the validation plan working with various subsystems owners. Define and develop the required bringup tools and automation scripts. Lead the bringup tools/ scripts development effort.
- Lead the overall bring-up activity from day 1 the silicon arrives in lab. Collaborate with rest of the chip bringup teams, debug the issues, participate in root cause, provide quick workarounds when required.
- Collaborate with design, verification, DFT, PD, millicode, firmware teams during bringup readiness, and bringup phases.
- The lead will also participate in broader feature architecture/ uarch/ design discussions to create a comprehensive validation plan.
- Estimate the overall effort for validation
Required education
Bachelor's Degree
Preferred education
Master's Degree
Required technical and professional expertise
- 8 to 12 years of work experience in
- Experience with bringup & validation of silicon when silicon arrives from fab
- Experience with Security architecture- Self Boot engine, Secure boot, SPI, I2C, serial communication protocols, OTPROM, on-chip sensors, Test and Debug infrastructure for Processors/ SoCs
- Good understanding of clocks and reset architecture
- Experience in working with architecture/ FW/ SW teams
