bandgap references , Common-centroid layout, ADC DAC-related circuits, Parasitic effects, Amplifiers, LVS, physical verification sign-off flows, ESD and latch-up considerations, TSMC process nodes, Differential Pairs, Analog Mixed-Signal Layout Design, Interdigitation, ERC, Current Mirrors, DRC, Cadence Virtuoso, Device matching techniques, LDOs

shielding , Layout verification tools, Analog Custom Layout Design, Advanced process nodes foundry rules, Common centroid, TI Texas Instruments project environment, DRC LVS ERC EM IR checks, Cadence Virtuoso, ESD latch-up prevention, Matching symmetry, Guard rings

post-layout simulation, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout

Perl, Tcl, EDA Tools, Mentor Graphics, Cadence Virtuoso

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

Verification Tools, Caliber DRC, LVS verification, analog layout fundamentals, Virtuoso XL, ERC, Cadence LVS, scripting and automation