Shell, Perl, Cadence LVS, scripting knowledge in Skill, FinFet technology layout design, DRC limitations, Calibre physical verification flow, layout XL, debugging skills, layout design and verification tools, Cadence Virtuoso, GXL

matching , parasitic effects, Cadence Tools, IR drop, reference circuits, Calibre DRC, MXL, Quantus, EM, LVS DRC PEX EMIR verification flows, LVS, xACT, Voltus, Bandgap Oscillators, Xl, StarRC, EXL, GXL, LDOs

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

CMOS/FinFET Process Technology (28nm and below), Analog Mixed-Signal Layout, DRC/LVS/LPE Verification, Deep Submicron Effects Mitigation, ESD and Latch-Up Design, EM/IR and Power Routing Considerations

rc extraction , Programming Skills, full-custom circuit layout verification, advanced semiconductor technology, physical verification tools, EMIR analysis, mixed signal analog high speed layout, Cadence Virtuoso, Circuit Design, device physics