bandgap references , Common-centroid layout, ADC DAC-related circuits, Parasitic effects, Amplifiers, LVS, physical verification sign-off flows, ESD and latch-up considerations, TSMC process nodes, Differential Pairs, Analog Mixed-Signal Layout Design, Interdigitation, ERC, Current Mirrors, DRC, Cadence Virtuoso, Device matching techniques, LDOs

post-layout simulation, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout

matching , shielding , Tcl, Perl, Clock Routing, Resistance and capacitance reduction, EMIR simulations, Cadence Virtuoso, signal flow, High-Speed Analog Custom layout development, Mentor, Bias and Power routing

Cadence Virtuoso, EMIR simulations, Custom layouts, Mentor

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Verification Tools, Caliber DRC, LVS verification, analog layout fundamentals, Virtuoso XL, ERC, Cadence LVS, scripting and automation

Perl, Linux, Python, Tcl, EM, LVS, IR analysis, Calibre, physical signoff flows, ERC, DRC, Parasitic Extraction, Cadence Virtuoso

Analog layout design, Design verification tools, Signal planning, IR ESD, Voltage drop, Process design rules, Micro-floor planning, TSMC N3 technology, Electron migration, High speed SerDes layouts