Calibre, Analog Layout, Cadence Virtuoso XL, Design for Manufacturability Principles, Signal Integrity Analysis, Power Distribution Techniques

Shell, Perl, Cadence LVS, scripting knowledge in Skill, FinFet technology layout design, DRC limitations, Calibre physical verification flow, layout XL, debugging skills, layout design and verification tools, Cadence Virtuoso, GXL

Synopsys StarRC, R3D, DRC, Mentor Graphics Calibre, LVS, Cadence Voltus, xACT, Cadence MXL

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

Cadence Tools, BCD process, Mentor Tools Calibre, Mixed Signal and Analog Layout, Dongbu PDK, layout of Analog blocks reference amplifier data converters