physical implementation, FinFET technologies, Analog Layout, Analog Mixed Signal Layout, advanced node designs

Analog layout design, Cadence Tools, FinFet experience, Debugging DRC, LVS, RF layout, Analog layout concepts for deep sub-micron processes, Floorplan, TSMC processes, Top-level integration, and antenna errors

layout verification , ICValidator, multiple layout design environments, FinFET, advanced packaging technologies, LVS, SOI, Calibre, mixed-signal layouts, Synopsys IC Compiler, high-speed layout techniques, statistical analysis tools, DRC, Parasitic Extraction, Mentor Graphics, TSMC PDKs, analog layout design, low-power design techniques, Cadence Virtuoso