ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

Cadence Tools, BCD process, Mentor Tools Calibre, Mixed Signal and Analog Layout, Dongbu PDK, layout of Analog blocks reference amplifier data converters

Verification Tools, Caliber DRC, LVS verification, analog layout fundamentals, Virtuoso XL, ERC, Cadence LVS, scripting and automation