shielding , Layout verification tools, Analog Custom Layout Design, Advanced process nodes foundry rules, Common centroid, TI Texas Instruments project environment, DRC LVS ERC EM IR checks, Cadence Virtuoso, ESD latch-up prevention, Matching symmetry, Guard rings

post-layout simulation, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout

matching , shielding , Tcl, Perl, Clock Routing, Resistance and capacitance reduction, EMIR simulations, Cadence Virtuoso, signal flow, High-Speed Analog Custom layout development, Mentor, Bias and Power routing

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

Cadence Virtuoso, EMIR simulations, Custom layouts, Mentor

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Perl, Linux, Python, Tcl, EM, LVS, IR analysis, Calibre, physical signoff flows, ERC, DRC, Parasitic Extraction, Cadence Virtuoso

Debugging Tools, Virtuoso XL, RMAP, Verification Tools, Caliber DRC, ERC, Cadence LVS, LVS verification