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Position: Analog Layout Engineer
Location: Hyderabad, India
Experience: 3+ Years
Job Requirements:
Responsibilities:
Mandatory Skill:
If you're planning to post this for hiring, I can also make it recruiter-ready with preferred nodes (e.g., TSMC 28nm/16nm/12nm/7nm) and specific analog IP requirements.
Interested please share your resume to [Confidential Information]
Job ID: 149071631
Skills:
shielding , Custom layout design, Clock routing, Layout automation, Cadence Virtuoso Layout XL GXL, Signal flow optimization, Reliability Analysis, SKILL scripting, Parasitic minimization, Device matching, Symmetry
Skills:
shielding , Layout automation, Cadence Virtuoso Layout XL GXL, pegasus, DRC LVS tools, Calibre, Clock routing, Signal flow optimization, Reliability Analysis, SKILL scripting, Parasitic minimization, ICV, Device matching, Symmetry
Skills:
Matplotlib, Neural Networks, Clustering, Tensorflow, Pandas, Pytorch, Decision Trees, Python, Cadence Virtuoso Layout Suite, Regression techniques, scikit-learn, Analog layout concepts, DRC LVS verification, Machine learning concepts, Graphs, EM IR analysis, Parasitic Extraction
Skills:
Python Scripting, Ant, DRC, EMIR awareness, Dfm, LVS, Cadence Virtuoso, ERC
Skills:
Routing, Circuit Design, Digital Implementation System, Floor Planning, design rule checking drc, Calibre
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