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About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As an Analog Layout Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects.What You Can Expect
Design and implementanalog layout blockssuch as PLLs, ADC/DAC, LDOs, VCOs, andhigh‑speedinterface circuits
Apply advanced layout techniques includingdevice matching, symmetry, and common centroid structures
Optimizelayouts forparasitics, performance, and area efficiency
Performfloorplanning, placement, and routingof complex analog/mixed‑signalblocks
EnsureDRC, LVS, and ERC clean layoutsand support fullsign‑offactivities
Working closely with team members to ensure alignment and successful project delivery.
Performpost‑layoutverification, includingPEX, EM/IR, and reliability analysis
HandleECO changesand actively supporttape‑outactivities
What We're Looking For
Bachelor's or master'sdegree (BE/B.Techor MS/M.Tech) in Electronics & Communication, Electrical & Electronics Engineering, or related field from a reputed institution
4-6 years of strong experience inhigh‑speedanalog,mixed‑signal, and custom layout design
Good understanding ofelectrical fundamentals and layout behavior, especially in advanced nodes
Reasonable knowledge onlocal device effects (LDE)and their impact on circuit performance
Expertisein device matching and symmetry, signal flow optimization, clock routing, shielding, parasitic minimization
Fairunderstanding of reliability aspects including EM/IR effects,latch‑upprevention, ESD protection, and power planning
Strong foundationin analog layout fundamentals, including matching, shielding, guard rings, and LOD/WPE effects
Good knowledge ofparasitic effects andhigh‑speedlayout practices
Experience withadvanced technology nodes(e.g.,A14,2nm,3nm,5nm) is a plus
ProficiencyinCadence Virtuoso (Layout XL / GXL)
Familiarity withDRC/LVS tools(Calibre,ICV,Pegasus, etc.)
Ability to handle designs acrossmultiple abstraction levels(cell → block → macro)
Exposure tolayout automation or SKILL scriptingis an added advantage
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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Marvell Technology, Inc. is an American company, based in Delaware, which develops and produces semiconductors and related technology. Founded in 1995, the company had more than 6,000 employees as of 2013,[2] and 10,000 patents worldwide and annual revenue of $2.9 billion (FY19). Its U.S. headquarters is located in Santa Clara, California
Job ID: 148333403
Skills:
Synopsys StarRC, R3D, DRC, Mentor Graphics Calibre, LVS, Cadence Voltus, xACT, Cadence MXL
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