shielding , Custom layout design, Clock routing, Signal flow optimization, Power ground routing methodologies, Parasitic RC minimization, Mentor Graphics, EM IR analysis, Cadence Virtuoso, Device matching, Biasing strategies

Matplotlib, Neural Networks, Clustering, Tensorflow, Pandas, Pytorch, Decision Trees, Python, Cadence Virtuoso Layout Suite, Regression techniques, scikit-learn, Analog layout concepts, DRC LVS verification, Machine learning concepts, Graphs, EM IR analysis, Parasitic Extraction

shielding , Layout automation, Cadence Virtuoso Layout XL GXL, pegasus, DRC LVS tools, Calibre, Clock routing, Signal flow optimization, Reliability Analysis, SKILL scripting, Parasitic minimization, ICV, Device matching, Symmetry

Python Scripting, Ant, DRC, EMIR awareness, Dfm, LVS, Cadence Virtuoso, ERC

Routing, Circuit Design, Digital Implementation System, Floor Planning, design rule checking drc, Calibre

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques