Calibre, Analog Layout, Cadence Virtuoso XL, Design for Manufacturability Principles, Signal Integrity Analysis, Power Distribution Techniques

Shell, Perl, Cadence LVS, scripting knowledge in Skill, FinFet technology layout design, DRC limitations, Calibre physical verification flow, layout XL, debugging skills, layout design and verification tools, Cadence Virtuoso, GXL

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Layout Techniques, Analog Layout Design

Analog layout design, Design verification tools, Signal planning, IR ESD, Process design rules, Voltage drop, Micro-floor planning, TSMC N3 technology, Electron migration, High speed SerDes layouts

CMOS/FinFET Process Technology (28nm and below), Analog Mixed-Signal Layout, DRC/LVS/LPE Verification, Deep Submicron Effects Mitigation, ESD and Latch-Up Design, EM/IR and Power Routing Considerations