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Analog Layout Engineer |5-8 Yrs | Immediate Joiners ,Bangalore
C
Analog Layout Engineer |5-8 Yrs | Immediate Joiners ,Bangalore
CapgeminiEarly Applicant
- Posted 14 hours ago
- Be among the first 10 applicants
Job Description
We are looking for talented Analog Layout Engineers with strong experience in advanced FinFET technologies to join a leading semiconductor project for a global client.
Key Requirements
5-8 years of relevant Analog Layout experience
Expertise in FinFET technologies (7nm / 3nm)
Strong understanding of Analog/Mixed Signal Layout concepts
Experience working on advanced node designs and physical implementation
Candidates from non-Intel client projects preferred
Additional Information
- Immediate to short joiners (0-30 days) will be given preference.
- Work Location: Bangalore.
More Info
Key Skills
physical implementation
FinFET technologies
Analog Mixed Signal Layout
advanced node designs
About Company
Skills:
analog filters , test equipment , Circuit Design, SPICE Simulation, Signal Integrity, Transistor Modeling, Pcb Layout, RF Design, power management, Noise Analysis
Early Applicant
Skills:
Test Station Development (TSD), Statistical Process Control (SPC), Continuous Integration (CI) for hardware test, RF and low-frequency analog/digital signals, Electrical design simulation, Yield debug, Optical measurement principles, Production data analysis, Mentoring junior engineers, Schematic layout support
Skills:
Debugging, Physical Verification Tools, PEX, FinFET, LVS, Layout Optimization, ERC, DRC, Post-layout Verification, Analog Custom Layout, High-performance Analog Mixed-Signal Blocks, Advanced Technology Nodes, Cadence Virtuoso
Skills:
Dll, Dac, ADC, FinFET process technologies, Voltage detectors, silicon debug, Oscillators, Voltage and current references, Mixed-mode simulations, Pll, Simulation of analog blocks, power management, Clock management, characterization, Statistical simulations, Switching regulators, Signal Processing
Skills:
Routing, DC-DC Converter, Layout optimization, High Voltage BCD Power Management technologies, Analog Mixed-Signal Layout, LVS, ERC extraction, Latch-up prevention, Calibre, Isolation structures, DRC, Floor Planning, LDO, Cadence Virtuoso, Guard rings, PMIC, Device placement