analog filters , test equipment , Circuit Design, SPICE Simulation, Signal Integrity, Transistor Modeling, Pcb Layout, RF Design, power management, Noise Analysis

Test Station Development (TSD), Statistical Process Control (SPC), Continuous Integration (CI) for hardware test, RF and low-frequency analog/digital signals, Electrical design simulation, Yield debug, Optical measurement principles, Production data analysis, Mentoring junior engineers, Schematic layout support

Debugging, Physical Verification Tools, PEX, FinFET, LVS, Layout Optimization, ERC, DRC, Post-layout Verification, Analog Custom Layout, High-performance Analog Mixed-Signal Blocks, Advanced Technology Nodes, Cadence Virtuoso

Dll, Dac, ADC, FinFET process technologies, Voltage detectors, silicon debug, Oscillators, Voltage and current references, Mixed-mode simulations, Pll, Simulation of analog blocks, power management, Clock management, characterization, Statistical simulations, Switching regulators, Signal Processing

Routing, DC-DC Converter, Layout optimization, High Voltage BCD Power Management technologies, Analog Mixed-Signal Layout, LVS, ERC extraction, Latch-up prevention, Calibre, Isolation structures, DRC, Floor Planning, LDO, Cadence Virtuoso, Guard rings, PMIC, Device placement