Design Engineer
Design Engineer
smartsoc solutions pvt ltd- Posted 13 hours ago
- Be among the first 10 applicants
Job Description
- 4+ years of experience in Analog and mixed signal design
- Should have hands-on experience in designing analog blocks for any of the following domains:
- Power management (voltage and current references, voltage detectors, linear and/or switching regulators)
- Clock management (oscillators, PLL, DLL)
- Signal processing (ADC, DAC)
- Should have solid understanding of CMOS and FinFET process technologies and associated issues in deep sub-micron technologies i.e. 28nm, 16nm and smaller.
- Should have hands-on experience in simulation of analog blocks, mixed-mode simulations, statistical simulations etc.
- Knowledge in scripting (PERL, TCL, etc.) and modelling (Matlab, VerilogA, etc.) tools will be an advantage
- Should have good insight into layouts
- Silicon debug/characterization experience is an advantage
- Should possess good documentation, communication and presentation skills
- Experience of working in a multi-site environment
Interested candidate please share the updated resume to [Confidential Information]
Location : Bangalore
Notice period :0-30 days
Qualification:
B.E./B.Tech/M.E./M.Tech in ECE / VLSI / Electrical / Electronics Engineering
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
FinFET process technologies
Voltage detectors
Voltage and current references
Mixed-mode simulations
Simulation of analog blocks
Clock management
Statistical simulations
Switching regulators
About Company
Skills:
Design Rule Checks (DRC), Layout-versus-Schematic (LVS), Analog Circuit Design, Post-silicon debug, Custom Layout, Floor Planning, Foundry-specific design guidelines, Analog Layout Design, Device matching, Parasitic-aware layout optimization
Skills:
bandgap references , static timing analysis, Verilog, PLLs, Synthesis, Clock-domain crossing CDC, Oscillators, ADCs, Low-power design fundamentals, systemverilog, Reset-domain crossing RDC, FSM design, Rtl Design, DACs, Timing Concepts, LDOs
Skills:
simulation and verification flow, DFT design and verification, silicon bringup, DFT technologies, fault modeling, ASIC DFT synthesis, IP integration, DFT specification definition, silicon debug activities
Skills:
Phase Interpolator, CAD tools for circuit simulation, Cadence tool experience, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification
Skills:
Bias generators, Bandgaps, Simulation verification, Cadence Virtuoso Spectre, ADCs, SPICE-based simulations, Analog Circuit Design, Power-management ICs, DRC LVS extraction, MOSFET physics, DACs, Silicon debug support, Driver amplifiers, DC-DC converters, Post-layout verification, Sensing circuits, Gate drivers, Error amplifiers, Charge pumps, LDOs, Level shifters, Analog Layout