AMS Verification
AMS Verification
ciliconchip- Posted 10 days ago
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Job Description
AMS / Mixed-Signal Verification Engineer
Location: Bangalore, India
Experience: 2+ Years
Notice Period: Immediate to 60 Days
Role Overview
We are looking for a hands-on AMS / Mixed-Signal Verification Engineer to design, verify, and debug complex mixed-signal IPs (such as ADCs, DACs, LDOs, PLLs, SerDes, and GPIOs). You will work closely with design teams to build scalable testbenches, run co-simulations, and ensure functional coverage closure.
Key Responsibilities
- Behavioral Modeling: Develop block-level models using Verilog-AMS, SystemVerilog, or Real Number Modeling (RNM) for top-level mixed-signal simulations.
- Testbench Development: Build and maintain UVM-based testbenches, automated checkers, and constrained-random test environments.
- Co-Simulation: Run SPICE + Digital co-simulations for key AMS IPs.
- Debug & Coverage: Analyze waveform mismatches (WaveView, SimVision), debug interface/corner-case failures, and drive functional coverage to closure.
Key Requirements
- Experience: 2+ years of hands-on experience in AMS/Mixed-Signal design verification and debug.
- Languages & Methodologies: SystemVerilog, UVM, Verilog-AMS, SVA (SystemVerilog Assertions), and RNM (Real Number Modeling / WREAL).
- Tools Exposure:
- EDA Tools: Cadence Virtuoso, ADE Assembler, Xcelium/AMS, DiscoveryAMS, or Synopsys XA / PrimeSim.
- Debug/Regression: ViVA, SimVision, WaveView, vManager.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
ADE Assembler
Xcelium
WaveView
AMS DiscoveryAMS
vManager
Digital co-simulations
Verilog-AMS
ViVA
PrimeSim
Synopsys XA
About Company
Skills:
Real Number Modeling (RNM), Verification Coverage Analysis, Cadence Xcelium, coverage analysis, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, PLL Verification, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Cadence ADE Assembler, Analog Mixed-Signal Verification, Mixed-Signal Testbench Development, Cadence Mixed-Signal Design Environment, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Simulation Debugging, Analog Building Blocks, AMS Verification, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology
Skills:
simvision , Perl, Shell scripting, Python, Tcl, Xcelium, VIVA, VerilogAMS, Virtuoso ADE Assembler, SV RNM, System Verilog UVM, Regression flows
Skills:
System Verilog, Visual Studio Code, GitHub Copilot, Mixed-Signal verification, Hspice, Uvm, Cadence Xcelium-AMS, Spectre
Skills:
Perl, Python, Tcl, Synopsys VCS AMS, SystemVerilog Wreal, regression verification, Cadence AMS Designer, Xcelium, Verilog-AMS, mixed-signal testbenches, Spectre