AMS Verification
AMS Verification
ALTEN Calsoft Labs- Posted a month ago
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Job Description
AMS Verification Engineer
Experience: 3 to 5 Years
Location: Bangalore
Job Description
- Perform Analog Mixed-Signal (AMS) verification using SystemVerilog, Wreal, and Verilog-AMS for IP and subsystem-level designs.
- Develop and maintain mixed-signal testbenches, behavioral and real-number models (RNM) for analog/digital interfaces.
- Drive functional and regression verification, ensuring coverage closure and model-to-SPICE correlation.
- Collaborate closely with analog and digital design teams to debug AMS integration and simulation issues.
- Hands-on experience with Cadence AMS Designer, Xcelium, Spectre, or Synopsys VCS AMS.
- Good understanding of analog concepts such as PLLs, ADC/DACs, SerDes, or Power Management IPs.
- Scripting skills in Python, Perl, or TCL for automation and flow enhancements are preferred.
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Key Skills
About Company
Skills:
simvision , ADE Assembler, Xcelium, WaveView, AMS DiscoveryAMS, Uvm, systemverilog, vManager, Digital co-simulations, Verilog-AMS, ViVA, Spice, PrimeSim, Cadence Virtuoso, Synopsys XA
Skills:
Real Number Modeling (RNM), Verification Coverage Analysis, Cadence Xcelium, coverage analysis, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, PLL Verification, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Cadence ADE Assembler, Analog Mixed-Signal Verification, Mixed-Signal Testbench Development, Cadence Mixed-Signal Design Environment, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Simulation Debugging, Analog Building Blocks, AMS Verification, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology
Skills:
simvision , Perl, Shell scripting, Python, Tcl, Xcelium, VIVA, VerilogAMS, Virtuoso ADE Assembler, SV RNM, System Verilog UVM, Regression flows
Skills:
System Verilog, Visual Studio Code, GitHub Copilot, Mixed-Signal verification, Hspice, Uvm, Cadence Xcelium-AMS, Spectre