Real Number Modeling (RNM), Verification Coverage Analysis, Cadence Xcelium, coverage analysis, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, PLL Verification, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Cadence ADE Assembler, Analog Mixed-Signal Verification, Mixed-Signal Testbench Development, Cadence Mixed-Signal Design Environment, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Simulation Debugging, Analog Building Blocks, AMS Verification, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology

simvision , Perl, Shell scripting, Python, Tcl, Xcelium, VIVA, VerilogAMS, Virtuoso ADE Assembler, SV RNM, System Verilog UVM, Regression flows

System Verilog, Visual Studio Code, GitHub Copilot, Mixed-Signal verification, Hspice, Uvm, Cadence Xcelium-AMS, Spectre

Perl, Python, Tcl, Synopsys VCS AMS, SystemVerilog Wreal, regression verification, Cadence AMS Designer, Xcelium, Verilog-AMS, mixed-signal testbenches, Spectre