hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, test benches, Rtl Design, UVM verification flow, Synthesis, Timing Closure, Verification, Debug, Simulation

Pcie, Usb, Tcl, FPGA Design, Ethernet, Vcs, Debugging, Python, DDR, digital system design, Xilinx Vivado, Timing Analysis, systemverilog, clock domain crossing, Hardware Verification, FPGA toolchains, in-circuit emulators, Oscilloscopes, Questa, Intel Quartus, Resource Optimization, Modelsim, logic analyzers, VHDL, Lattice Diamond

Scripting, Tcl, Verilog, FPGA Design, Ethernet, Vcs, Debugging, Digital Logic Design, Python, Bash, Pcie, Questa, FPGA synthesis, systemverilog, Xcelium, CXL, Axi, DDR4, Simulation Tools, DDR5, high-speed interfaces, LPDDR5, Timing Closure, LPDDR4, Altera Quartus Prime Pro

memory controllers , Spi, Uart, Verilog, I2c, Pcie, Hdl Languages, Libero, Unix Systems, Uvm, Otn, systemverilog, Microsemi FPGAs, Ethernet-based protocols, Vivado, quartus, scripting tools, VHDL, VMM, Axi

Hdl, VHDL

Jtag, Fpga, Xilinx, Simulation, RTL