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Job Title: Senior STA Engineer (Static Timing Analysis)
Location: Hyderabad
Experience: 5+ years
At Best Nanotech, we are pushing the boundaries of Moore's Law. Our silicon powers the world's most advanced [Product Type, e.g., Data Centers/Smartphones]. Our Physical Design team is looking for a timing expert to own the sign-off convergence for our latest SoC.
The Role As an STA Engineer, you will be the gatekeeper of performance. You will be responsible for full-chip and block-level timing analysis and closure. You will work closely with the PD and RTL design teams to debug complex timing paths and drive the design to tape-out.
Key Responsibilities
What We Need (Requirements)
Nice to Have
Ready to Join Click Apply Now to start the conversation or email [Confidential Information]
Job ID: 136626003
Skills:
Tcl, Python, Perl, RTL to GDSII, LVF POCV variation formats, Constraint Generation, STA Static Timing Analysis, Cadence Tools, Tweaker Prime Time, Automation scripts, Timing ECO Implementation, Timing Closure, Timing Analysis, Digital design Implementation
Skills:
power optimization , python, perl, Routing, Tcl, CTS, Signoff checks, Timing ECOs, Timing Analysis and Closure, EM, DFT insertion, IR flows, Scan DFT modes, RTL to GDS, Physical Verification, Extraction, Placement, Timing Constraints Development, Check Timing Analysis, Floor-planning, Digital Synthesis, Check Design
Skills:
EDA tool, Sta, DFT modes requirements, SDC constraints, TCL/scripting, SDC construct
Skills:
Routing, Perl scripting, Crosstalk avoidance, CTS, High frequency Datapath intensive Cores, Power Estimation, Deep sub-micron design problems, Tempus, Optimization, Constraint generation and validation, primetime, Physical Synthesis, Placement, Clock Tree Synthesis, Floor-planning, Multi voltage design convergence, Clocking architecture
Skills:
synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, path-based analysis, jitter, false paths, Timing Closure, AOCV, skew
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