Job Title: Senior STA Engineer (Static Timing Analysis)
Location: Hyderabad
Experience: 5+ years
At Best Nanotech, we are pushing the boundaries of Moore's Law. Our silicon powers the world's most advanced [Product Type, e.g., Data Centers/Smartphones]. Our Physical Design team is looking for a timing expert to own the sign-off convergence for our latest SoC.
The Role As an STA Engineer, you will be the gatekeeper of performance. You will be responsible for full-chip and block-level timing analysis and closure. You will work closely with the PD and RTL design teams to debug complex timing paths and drive the design to tape-out.
Key Responsibilities
- Sign-off Ownership: Perform Static Timing Analysis (STA) from netlist to tape-out using industry-standard tools.
- Constraint Management: Develop and validate SDC (Synopsys Design Constraints) for complex multi-mode multi-corner (MMMC) designs.
- Timing Closure: Analyze and fix Setup, Hold, Transition, and Pulse Width violations.
- Signal Integrity: Analyze crosstalk (SI), noise, and OCV (On-Chip Variation) effects at advanced nodes (7nm and below).
- ECO Implementation: Generate and implement functional and timing ECOs to fix critical paths.
- Automation: Write Tcl/Python scripts to automate flows and improve analysis efficiency.
What We Need (Requirements)
- Education: B.Tech/M.Tech in Electronics, Electrical Engineering, or VLSI.
- Tool Proficiency: Strong hands-on experience with Synopsys PrimeTime (preferred) or Cadence Tempus.
- Tech Nodes: Experience working on deep sub-micron technology nodes (16nm, 7nm, 5nm).
- Technical Depth: Solid understanding of digital logic, CMOS circuit design, standard cell libraries, and latch-based designs.
- Scripting: Proficiency in Tcl, Perl, or Python for data parsing and flow automation.
Nice to Have
- Experience with Power Analysis (Voltage Drop / IR Drop) using RedHawk or Voltus.
- Knowledge of hierarchical timing budgeting and low-power design techniques (UPF/CPF).
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