Unix, Bug Tracking, Makefile, Shell, Configuration Management, PERL, Python, Verification dashboarding tools, Random stimulus, ARM CPU, PCI Express, Uvm, Functional coverage, systemverilog, AMBA bus protocols, Ethernet bus protocols

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

System Verilog, HBM4, Assertion-based verification, Cadence Xcelium, Power-aware verification, silicon debug, Crypto Network-on-Chip NoC, Formal-based verification, DRAM Memory Controller IPs, Gate-level simulation, Uvm, Synopsys VCS, Asic Design Verification, Synopsys JasperGold, Verification management tools, VC Formal, LPDDR6

C, Uart, Spi, Pcie, I2c, verification methodologies, assertion-based verification, coverage-driven verification, constrained-random testing, SystemVerilog UVM, Axi, SoC Verification, APB, AHB, simulation and debugging tools from Synopsys

Unix, Bug Tracking, Makefile, Configuration Management, Shell, PERL, System Verilog, Python, Random stimulus, ARM CPU, Checkers, PCI Express, Uvm, Assertions, AMBA bus protocols, Ethernet bus protocols, Functional verification environments, Scoreboards, Monitors

SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification

C, Perl, Computer Architecture, Ruby, Python, Assembly start up code, Makefiles, Stimulus generation, Uvm, Testbenches, Pre-silicon verification, Formal verification methods, Linker scripts, Post-silicon FPGA validation

Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification