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Design Verification Engineer

Design Verification Engineer

Chip Logic Technologies
5-7 Years
Not Disclosed
  • Posted 7 hours ago
  • Be among the first 10 applicants

Job Description

Company Description Chiplogic Technologies (Chiplogic) is an IP and product engineering services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML solutions. The organization delivers high-quality, dependable engineering services, supporting customers from concept to silicon. Chiplogic provides Offshore Development Center (ODC) and full turnkey semiconductor design and system solutions, including proof-of-concept (POC) projects. The company also offers IoT system solutions and AI/ML services built around its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework, enabling advanced video and real-time analytics applications.

Role Description The Design Verification Engineer Senior role is a full-time, on-site position based in Bengaluru. Key Responsibilities
  • Develop and execute verification plans for complex SoC designs.
  • Build and maintain SystemVerilog/UVM-based verification environments.
  • Develop test cases using SystemVerilog, UVM and C.
  • Perform SoC-level verification, subsystem verification and integration testing.
  • Work with standard interfaces and protocols such as AXI, AHB, APB, PCIe, I2C, SPI or UART.
  • Debug simulation failures and perform functional and code coverage analysis.
  • Collaborate with RTL design, architecture and software teams to achieve verification closure.
Required Skills
  • Minimum 5 years of hands-on Design Verification experience.
  • Strong experience in SoC verification and C-based verification.
  • Proficiency in SystemVerilog, UVM and assertion-based verification.
  • Experience with simulation and debugging tools from Synopsys, Cadence or Siemens EDA.
  • Good understanding of coverage-driven verification, constrained-random testing and verification methodologies.
  • Strong debugging, analytical and communication skills.

  • More Info

    Key Skills

    verification methodologies

    assertion-based verification

    coverage-driven verification

    constrained-random testing

    SystemVerilog UVM

    simulation and debugging tools from Synopsys

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