simvision , Perl, Shell scripting, Python, Tcl, Xcelium, AMs, VIVA, Virtuoso ADE, Assembler, SOC-AMS, VerilogAMS, SV UVM

Real Number Modeling (RNM), Verification Coverage Analysis, Analog Mixed-Signal Verification, Cadence Xcelium, coverage analysis, Mixed-Signal Testbench Development, DAC Verification, Cadence Mixed-Signal Design Environment, Root-Cause Analysis, Mixed-Signal Waveform Analysis, Mixed-Signal Simulation, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, PLL Verification, Simulation Debugging, ADC Verification, Analog Building Blocks, Regression Debugging, Mixed-Signal Interfaces, Verilog-AMS, Cadence Virtuoso, AMS Verification Methodology, Cadence ADE Assembler

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Python, Incisive, IMC, constrained randomization, behavioral modelling, metric driven, Uvm, ASIC design methodology, Spectre, System Verilog RNM, xCelium, vManager, assertions, VerilogAMS, mixed signal verification

Synopsys VCS, Cadence Xcelium, EDA Tools, Verilog-AMS, SV-RNM, Uvm, Verilog-A, systemverilog, Spectre

automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

Python, systemverilog, Analog Mixed-Signal circuits, EDA Tools, Cadence, Verilog-A

simvision , Cadence Xcelium, AMS SPICE, DMSO, verification planning, testcase creation, testbench development, Verisium, simulation debug, Cadence Virtuoso, Xps, Spectre UltraSim, analog mixed-signal simulation