Vcs, hardware emulation, FPD-Link, regression management, Xcelium, Palladium, JasperGold, formal verification tools, assertion-based verification, Uvm, CI CD, Ethernet PHY, systemverilog, automotive functional safety, SERDES, ISO 26262, Protium, Verilog-AMS, Questa, VC Formal, SVA, functional coverage

Pcie, Ethernet, Debugging, Test Planning, Coverage, DDR Memory Interfaces, Design Verification, Uvm, testbench development, systemverilog, RTL and functional verification

code coverage , Verilog, Debugging, FPGA Design, Scripting, Regression Testing, Vcs, systemverilog, Uvm, Testbench Development, Simulation Tools, Functional Verification, Timing Analysis, SoC Verification, Verification Plan, Verdi

Verilog, VHDL, simulation debugging, DO-254, traceability validation methodologies, coverage-driven verification, systemverilog

Java, Pcie, Perl, Verilog, Python, System Verilog, coverage-based verification methodology, assertions, Intel Quartus, Uvm, Xilinx Vivado

Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim

Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification

clocking , Ovm, DDR, Pcie, Verilog, Ethernet, Platform bring up in Emulators or Silicon, SOC boot flow, Constrained-random verification environments, Uvm, systemverilog, Power management flows, C SV tests, Low Power Verification, Coverage report generation, System Verilog Assertions, RTL GLS level simulations