SRAM ROM Memory IP Layout, Full-Custom Layout, DRC LVS ERC, Memory Layout Custom Layout, Cadence Virtuoso

caliber , Verification Tools, Layout Design, Cadence Virtuoso

Analog layout design, Cadence Tools, FinFet experience, Debugging DRC, LVS, RF layout, Analog layout concepts for deep sub-micron processes, Floorplan, TSMC processes, Top-level integration, and antenna errors

guard rings, PEX, Reliability, dummy structures, symmetry shielding, LVS, advanced-node custom layout, matching performance, ERC, DRC, matching-critical layouts, common-centroid interdigitation, Cadence Virtuoso, 2nm 3nm 5nm FinFET

matching , Routing, Parasitics, Memory Array Layout, Sram, LVS, NVM, Physical Verification, Calibre, floorplanning, Layout Optimization, Custom Layout, Memory Layout, Cadence Virtuoso, Placement, ERC, Hierarchical Layout, DRC, FinFET Technology, PPA Optimization, Memory Compiler, Rom

scripting expertise, Verification Tools, Cadence LVS, layout XL, Calibre physical verification, EXL, Cadence Virtuoso, GXL

matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS