Physical Verification sign-off flows and tools, PDK concepts, Physical Design implementation flow, Fusion Compiler, Foundry PDKs, ICC2, Tech LEF Design Rules, debugging and problem-solving skills, layouts, SVRF rule decks, Calibre, Innovus, backend design methodologies, ICV

IC Validator, Physical Verification, Calibre ICV, pegasus, DRC, ESD Verification, LVS, 3D IC Design

PV fixing, Esd, DRC, Innovas

Samsung foundries, TSMC, Physical Verification, PERC, advanced technology nodes, DRC, Antenna, Arm CPU designs, LVS, Dfm

Perl, Python, Tcl, Calibre, Physical Verification, ERC, DRC, LVS, Dfm, Density

Linux, Perl, UNIX, Tcl, Calibre, C-shell, ICV

Perl, Python, Tcl, Siemens Calibre, PERC, Calibre Interactive, TVF, Cadence Pegasus, EDA visualizer, LVS, CalibreDRV, Calibre DesignRev scripting, DRC, Tk, design for manufacturing, Cadence Virtuoso, SVRF

OASIS, Python, Shell, Perl, Tcl, PERC, LVS, CDL, Dfm, SVRF-based automation, Verilog netlists, XOR methodologies, layout connectivity, antenna density, ASIC physical verification, Spice, Cadence Pegasus, DEF, LEF, Siemens Calibre nmDRC, metal-fill, ERC, DRC, Synopsys ICV, GDSII