Physical Verification Engineer
Physical Verification Engineer
ALTEN Calsoft LabsEarly Applicant
- Posted a month ago
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Job Description
Experience of 5+ years in Physical verification and closure.
Location: Bangalore
NP - Immediate
Main responsibility of the candidate will be around achieving a clean GDS view with below key items:
Physical Verification closure for Arm CPU implementation:
- Should have completed multiple tape-outs with Physical Verification closure role in the past
- Strong understanding of DRC/LVS/PERC/Antenna/DFM and associated concepts for advanced
- nodes on TSMC and Samsung foundries
- Needs to run Physical Verification on Arm CPU designs on advanced technology nodes
- Needs to run fixing for DRC/LVS/PERC/Antenna/DFM on base/metal layers and give recommendation for P& R tool flow
- Good knowledge of advanced technology nodes like Samsung foundry (4nm/3nm) is extremely useful
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Samsung foundries
TSMC
PERC
advanced technology nodes
DRC
Arm CPU designs
About Company
Skills:
Scripting Languages, Perl, Tcl, Physical Verification sign-off flows and tools, PDK concepts, Physical Design implementation flow, Fusion Compiler, Foundry PDKs, ICC2, SVRF rule decks, Calibre, Innovus, ICV, Design Rules, Mixed-signal SOC environments, Backend design methodologies, Tech LEF, Custom IC design flows, Layouts, ESD reliability analysis, PERC methodologies
Skills:
IC Validator, Physical Verification, Calibre ICV, pegasus, DRC, ESD Verification, LVS, 3D IC Design
Skills:
PV fixing, Esd, DRC, Innovas
Skills:
Perl, Python, Tcl, Siemens Calibre, PERC, Calibre Interactive, TVF, Cadence Pegasus, EDA visualizer, LVS, CalibreDRV, Calibre DesignRev scripting, DRC, Tk, design for manufacturing, Cadence Virtuoso, SVRF