Role Overview
We are looking for a
Physical Verification Engineer with strong expertise in
full-chip and block-level physical verification for advanced technology nodes. The ideal candidate should have hands-on experience in
DRC, LVS, ERC, and Physical Verification signoff using industry-standard EDA tools while working closely with Physical Design, Layout, and Foundry teams.
Key Responsibilities
- Perform block and full-chip Physical Verification (PV) signoff.
- Debug and resolve DRC, LVS, ERC, ANT, Density, and DFM violations.
- Execute PV flows using Calibre or equivalent EDA tools.
- Collaborate with Physical Design, Layout, and Foundry teams to achieve clean tapeout.
- Develop and maintain automation scripts using Tcl, Perl, or Python.
- Support multiple technology nodes including 28nm, 16nm, 7nm, 5nm, or below.
Requirements
Required Skills
- 5+ years of experience in Physical Verification.
- Strong expertise in DRC, LVS, ERC, ANT, Density, DFM, and Signoff.
- Hands-on experience with Mentor Calibre (DRC/LVS/PERC) or equivalent PV tools.
- Good understanding of IC layout, CMOS process, and semiconductor manufacturing.
- Experience with advanced technology nodes (16nm/7nm/5nm or below).
- Scripting knowledge in Tcl, Perl, or Python.
- Strong debugging, analytical, and problem-solving skills.
Preferred Skills
- Experience with PERC, ESD/Latch-up verification.
- Exposure to FinFET technology and foundry signoff flows (TSMC/Samsung/Intel/GlobalFoundries).
- Knowledge of Physical Design flow and tapeout methodology.
Education: BE/B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related discipline.