Real Number Modeling, Verification Coverage Analysis, coverage analysis, Cadence Xcelium, Mixed-Signal Testbench Development, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, PLL Verification, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Mixed-Signal Simulation, Simulation Debugging, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Verilog-AMS, AMS Verification, Cadence Virtuoso, AMS Verification Methodology, Cadence ADE Assembler

Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Python, Incisive, IMC, constrained randomization, behavioral modelling, metric driven, Uvm, ASIC design methodology, Spectre, System Verilog RNM, xCelium, vManager, assertions, VerilogAMS, mixed signal verification

monte carlo , Python, Functional Coverage, power management, Analog Mixed-Signal, Uvm, Assertions, systemverilog, Pvt, Verification Automation, Mixed-Signal Debug, RNM, AMS Verification, Verilog-AMS, Spice, AMS Simulation, PMIC

automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

Python, systemverilog, Analog Mixed-Signal circuits, EDA Tools, Verilog-A, Cadence

SV RNM, AMs, Dms, Verification

simvision , Cadence Xcelium, AMS SPICE, DMSO, verification planning, testcase creation, testbench development, Verisium, simulation debug, Cadence Virtuoso, Xps, Spectre UltraSim, analog mixed-signal simulation

Register models and firmware interaction, Calibration and link training flows, SerDes PHY architectures, Uvm, systemverilog