Debugging, Tcl, Verilog, Python, Perl, Mentor, Synopsys, Timing Analysis, systemverilog, EDA Tools, low-power design concepts, cdc, Rtl Design, Cadence, digital IP development, AHB, Synthesis, APB, Axi, RDC, AMBA protocols

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

Debugging, System Verilog, 5G LTE, Uvm, AMD Zynq RFSoC, FPGA RTL design, Wi-Fi, Sta, VHDL, high-speed packet processing, DSP fundamentals, 5G, Synthesis, Altera Agilex, Timing Closure, Wireless Communication

arm architecture , PERL, Python, Tcl, cdc, LINT, SoC level design integration, Digital Design, timing exceptions, writing UPF, Timing Constraints, design reuse, automation using scripting techniques, RTL Coding, designing with multiple power domains, CHI protocol

Verilog, Uvm, Synopsys VCS, VHDL, RTL design methodologies, Modelsim, Cadence Incisive

RDC, RTL coding expertise in Verilog, SpyGlass Lint, micro-architecture development, systemverilog, FSM design, Pipelining techniques, ASIC SoC design flow, Datapath architecture, cdc, Clock and Reset domain crossings

Pcie, Ethernet, Scripting, cdc, linting, design qualifications, Security Protocols, networking IP solutions, Verilog RTL design, Simulation