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3-8 Years
Not Disclosed
Early Applicant
  • Posted 2 months ago
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Job Description

Location: Hyderabad, India

Experience: 3 – 8 Years

Work Mode: Work From Office – Hyderabad

Project: Global Foundry Program

Job Summary

We are looking for a highly skilled RTL Design Engineer with strong experience in micro-architecture development and RTL implementation. The candidate will be responsible for converting architecture specifications into scalable and synthesizable RTL while ensuring high-quality design through SpyGlass lint and CDC sign-off.

This role offers the opportunity to work on a high-impact Global Foundry program, collaborating with cross-functional teams across design, verification, and synthesis.

Key Responsibilities

  • Convert architecture specifications into detailed micro-architecture design
  • Develop clean, synthesizable RTL using Verilog/SystemVerilog
  • Perform RTL quality checks using SpyGlass (Lint, CDC, RDC)
  • Design FSMs, datapath logic, and pipelined architectures
  • Ensure robust clock domain crossing (CDC) and reset domain crossing (RDC) handling
  • Collaborate with Design Verification (DV) teams to resolve functional issues
  • Work with synthesis and physical design teams for timing closure and implementation readiness
  • Follow low-power friendly RTL design practices
  • Ensure high-quality RTL sign-off for silicon readiness

Required Skills & Qualifications

  • Strong RTL coding expertise in Verilog/SystemVerilog
  • Hands-on experience with SpyGlass (Lint / CDC / RDC)
  • Experience in micro-architecture development
  • Good understanding of:
  • FSM design
  • Pipelining techniques
  • Datapath architecture
  • Clock and Reset domain crossings
  • Experience working with ASIC/SoC design flow

Good to Have

  • Exposure to AMBA protocols (AXI / AHB / APB)
  • Experience working on complex SoC designs
  • Familiarity with low power design methodologies

Why Join Us

  • Opportunity to work on global semiconductor programs
  • Exposure to advanced ASIC and SoC development
  • Collaboration with highly experienced engineering teams
  • Long-term career growth in chip design and semiconductor engineering

Location Note: This role is based in Hyderabad, and candidates should be open to working from the Hyderabad office.

More Info

Key Skills

RDC

Pipelining techniques

Datapath architecture

SpyGlass Lint

RTL coding expertise in Verilog

Clock and Reset domain crossings

micro-architecture development

ASIC SoC design flow

FSM design

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