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Location: Hyderabad, India
Experience: 3 – 8 Years
Work Mode: Work From Office – Hyderabad
Project: Global Foundry Program
Job Summary
We are looking for a highly skilled RTL Design Engineer with strong experience in micro-architecture development and RTL implementation. The candidate will be responsible for converting architecture specifications into scalable and synthesizable RTL while ensuring high-quality design through SpyGlass lint and CDC sign-off.
This role offers the opportunity to work on a high-impact Global Foundry program, collaborating with cross-functional teams across design, verification, and synthesis.
Key Responsibilities
Required Skills & Qualifications
Good to Have
Why Join Us
Location Note: This role is based in Hyderabad, and candidates should be open to working from the Hyderabad office.
Job ID: 144559121
Skills:
Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design
Skills:
Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design
Skills:
LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies
Skills:
memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram
Skills:
Tcl, Python Scripting, Perl, PrimeTime or equivalent tools, ASIC design flow, Low power digital design and analysis, ASIC design in sub-20nm technology nodes, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog
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