RTL Design Engineer

Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design

Perl, Verilog, Python, Tcl, VHDL, Static Verification, systemverilog, Rtl Design

LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram

Unix, Python, Shell, Linux, Skill, SoC Integration, Rtl Design