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RTL Design Engineer
HCL TechBee

RTL Design Engineer

HCL TechBee
7-12 Years
Not Disclosed
  • Posted 2 months ago
  • Be among the first 10 applicants

Job Description

We HCL are seeking a highly motivated RTL Design Engineer with 7-12 years of experience to join our growing team. You will play a vital role in the design and development of complex digital logic for next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in RTL design methodologies and verification.

Responsibilities:

  • Design and develop RTL code for digital logic blocks and modules using Verilog or VHDL
  • Perform comprehensive functional verification using industry-standard methodologies (e.g., UVM)
  • Conduct static timing analysis (STA) and participate in timing closure activities
  • Integrate designed modules into larger subsystems and ensure seamless functionality
  • Collaborate effectively with design, verification, and synthesis teams throughout the development cycle
  • Write clear, concise, and well-documented RTL code adhering to coding standards
  • Stay current with advancements in RTL design tools and methodologies

Qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
  • 7-12 years of solid experience in RTL design for ASICs or SoCs
  • In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
  • Proven ability to design and verify high-performance and efficient digital circuits
  • Expertise in Verilog or VHDL with a strong understanding of coding styles and best practices
  • Experience with simulation and verification tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS)
  • Familiarity with SDC (Standard Delay Constraint) format for timing analysis
  • Excellent problem-solving skills and a meticulous attention to detail
  • Strong communication and collaboration skills to work effectively in a team environment

Benefits:

  • Competitive salary and benefits package
  • Opportunity to work on leading-edge technologies and projects
  • Collaborative and dynamic work environment
  • Potential for professional development and career advancement

  • More Info

    Job Type:
    Permanent Job
    Industry:
    Other
    Function:
    Engineering
    Employment Type:
    Full time

    Key Skills

    Uvm

    Synopsys VCS

    Cadence Incisive

    VHDL

    RTL design methodologies

    Modelsim
    Verilog

    About Company

    Last Updated: 13-10-2026 10:31:30 PM

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