Ecos, routing, Perl, Python, Tcl, Sta, Synthesis, Design Compiler, CTS, primetime, Fusion Compiler, floorplanning, Asic Physical Design, setup hold closure, Placement, MCMM timing analysis, Synopsys ICC2

power optimization , routing, Perl, Verilog, Python, Tcl, Synthesis, submicron process node technologies, Timing Analysis, power delivery methodologies, LVS, Power Estimation, formal verification, VHDL, layout verification methods, DRC, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

Electronic design automation tools, Physical Design, Design for manufacturability, Placement and routing methodologies, Clock Tree Synthesis, Design rule checks, Timing closure techniques

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

layout verification , RTL Synthesis, DFT Implementation, EDA Tools

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

Tcl, static timing analysis, Python, Perl, routing, digital IC design, Dfm, LVS, Fusion Compiler, Placement, Innovus, floorplanning, advanced packaging, ICC2, Parasitic Extraction, Timing Closure, DRC, Dft, Clock Tree Synthesis, physical design sign-off

EM IR understanding and fixes, PV closure, Util area reduction experiments, Physical aware Synthesis using FC, ECO cycle, STA analysis, PnR-Floorplan Macro placement, Density Congestion Timing issues and fixes on lower tech nodes 5nm