Physical Design Engineer
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Physical Design Engineer
Location: Bengaluru
Experience: 4–10 Years
Role Overview
We are looking for a hands-on Physical Design Engineer to drive implementation and timing closure for complex ASIC/SoC designs.
Key Responsibilities
Core Technical Skills
Ideal Candidate: A technically strong Physical Design engineer with solid implementation and timing-closure experience, capable of owning blocks or full-chip activities through tapeout.
Job ID: 152936463
Skills:
static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, low-power design techniques, Place And Route, Clock Tree Synthesis
Skills:
redhawk , Scripting Languages, Python, Perl, Tcl, PrimeTime PT, voltage islands, Clock Tree Synthesis CTS, HM-level PV, Tempus, STA signoff checks, Fusion Compiler FC, Voltus, Innovus, Genus, IR drop analysis, Place Route PNR, ECOs for timing convergence, Tweaker, floorplanning, PDN design, low-power design methodologies, LEC low-power checks, Physical Verification, Physical Design, STA closure
Skills:
layout verification , System Verilog, Computer Engineering, Tcl, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs
Skills:
Physical Design, Design for manufacturability, Timing closure methodologies, Placement and routing techniques, Clock Tree Synthesis, Design rule checks
Skills:
routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow
