Physical Design Engineer
Physical Design Engineer
ALTEN Calsoft LabsThis job is no longer accepting applications
Job Description
Physical Design Engineer - Senior / Lead
Job Description:
- Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization.
- Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing closure, and physical design sign-off.
- Physical Design: Experience in floorplanning, placement, routing, clock tree synthesis (CTS), and static timing analysis (STA).
- Optimization: Focus on power, performance, and area (PPA) optimization.
- Sign-off: Conduct DRC, LVS, and parasitic extraction for clean designs.
- Advanced Process Nodes: Experience with 7nm, 5nm, or lower process nodes.
- Cross-functional Collaboration: Work closely with design, verification, and manufacturing teams.
- Tape-out: Drive tape-out process and ensure high-quality designs.
- Qualifications: Bachelor's or Master's degree in Electrical Engineering, with 5+ years of experience.
- Preferred: Experience with DFM, DFT, and advanced packaging technologies.
Additional Skills:
- Proficiency in scripting languages like TCL, Perl, or Python for automating design tasks.
- Excellent problem-solving skills and attention to detail.
- Strong communication skills and the ability to collaborate effectively in a team environment.
Experience: 4 to 8 years
Location: Bangalore / Hyderabad
More Info
Job Type:
Industry:
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Key Skills
Fusion Compiler
Innovus
advanced packaging
ICC2
DRC
physical design sign-off
About Company
Skills:
Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation
Skills:
C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation
Skills:
Physical Design Planning, Placement, Floor Planning
Skills:
layout verification , very large scale integration (VLSI) design, system on a chip (SoC), System Verilog, clock voltage domain crossing design for testing DFT, ASIC Design, design rules, low power designs
Skills:
Verilog, System Verilog, python, Perl, Sta, Synthesis, Physical Verification, CTS, DFT tools, Extraction, Timing Analysis, Place And Route, Cadence, Synopsys