redhawk , Shell, Python, Tcl, primetime, Fusion Compiler, Timing closure methodologies, ICC2, Asic Physical Design, Calibre, Innovus, Clock-tree synthesis

Routing, Python Scripting, Tcl Scripting, primetime, floorplanning, Tempus, Cadence Innovus, Calibre, Physical Verification, Physical Design, Timing Closure, Placement, ECO Implementation, ICV, Synopsys ICC2

PERL, Tcl, Sta, Synthesis, CTS, Place Route, Full-chip Floor-planning, RTL2GDSII flow, ICC2, Physical Verification, Tempus, Make scripting, layout closure, timing convergence, primetime, Innovus, Physical Design, Timing Closure, high frequency design methodologies

Soc, PD convergence, PV fixing, ASIC Design, scripting with TCL, EMIR fixing, Vlsi Design, PD methodologies, coding constraints

closure , Perforce, routing, Git, Python, Tcl, Synthesis, cdc, Extraction, PPA targets, hierarchical hard-macro integration, MBIST, Scan, UPF, Floorplan, custom macros, Dft, timing power ECOs, RTL-to-GDS flow, partitioning, CPF, SRAMs, Clock Tree Synthesis

Python, Tcl, Cadence Tools, EDA Tools, EM IR checks, Timing Closure, PDK management, low-power design, physical design methodology, foundry tapeout processes

Routing, Perl, Shell scripting, Python, Tcl, EM Analysis, floorplanning, Cadence Innovus, Signal Integrity, UPF, Noise Analysis, Power Planning, Calibre, Physical Verification, Placement, Timing Closure, Low-Power Design methodologies, CPF, Physical Design implementation, Synopsys Fusion Compiler ICC2

Linux Scripting, Python, AI GenAI systems, VLSI EDA tools, Agentic AI MCP RAG workflows, triaging and debugging complex software tool issues

redhawk , Perl, Tcl, Yaml, Sta, BaseDRC, Synthesis, CTS extraction, Fusion Compiler, Formality, LVS analysis, Timing Analysis, Place And Route, Power Efficiency techniques, primetime, Physical Verification, timing eco’s, EM fixes, DRC, ECO methodologies, ICV, Cadence Innovus flow