Senior Physical Design Engineer

Brief About Tech Mahindra – Silicon Engineering

Tech Mahindra Silicon Engineering is a key part of Tech Mahindra's semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, networking, and industrial clients. The practice focuses on VLSI, Embedded Systems, SoC Design, and Platform Engineering, supporting customers from architecture and RTL design through implementation, verification, validation, and post-silicon support.

The Silicon Engineering unit works across IP, Sub-System, and SoC-level development, offering deep expertise in areas such as Physical Design, RTL Design, Design Verification, DFT, Analog/Mixed-Signal Design, Post-Silicon Validation, Embedded Software, and System Engineering. Teams leverage industry-leading EDA tools and advanced implementation methodologies to deliver high-performance, low-power, and manufacturable silicon solutions.

Backed by Tech Mahindra's global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology companies worldwide, serving as an extended engineering arm to accelerate silicon development programs, optimize design quality, and enable faster time-to-market for next-generation SoCs and products.

About the Role – In this exciting role, you will be responsible for the implementation and physical realization of complex SoC, subsystem, and IP designs from netlist to GDSII. You will work closely with RTL, DFT, STA, and methodology teams to achieve timing, power, area, and reliability targets while ensuring robust and manufacturable silicon. The role involves floorplanning, placement, clock tree synthesis, routing, physical verification, timing closure, and signoff activities using industry-standard EDA tools.

Responsibilities – Key Responsibilities

• Execute complete Physical Design implementation flow from synthesis handoff to GDSII signoff.
• Develop and optimize Floorplan, Power Planning, and Power Grid Design for complex SoCs and IP blocks.
• Perform Placement, Clock Tree Synthesis (CTS), Routing, and Physical Optimization.
• Drive Timing Closure across setup, hold, recovery, removal, and noise constraints.
• Analyze and resolve Congestion, IR Drop, EM, Crosstalk, and Power Integrity issues.
• Perform Physical Verification including DRC, LVS, ERC, and Antenna checks.
• Work closely with STA, RTL, DFT, and Verification teams to ensure design convergence.
• Support low-power implementation methodologies including UPF/CPF, power gating, isolation, and retention strategies.
• Develop and maintain automation flows using TCL, Perl, Python, and Shell scripting.
• Perform signoff checks including STA, SI, IR/EM, and Physical Verification signoff.
• Participate in design reviews, technical discussions, customer interactions, and methodology improvements.
• Collaborate with global teams to meet project schedules, quality goals, and tape-out milestones.

Qualifications – BE/BTech/ME/MTech degree in Electronics, Electrical, Telecommunications, Microelectronics, VLSI Design, or related engineering disciplines.

Required Skills

• Strong experience in Physical Design implementation for advanced technology nodes.
• Expertise in Floorplanning, Power Planning, Placement, CTS, Routing, and Timing Closure.
• Hands-on experience with Cadence Innovus and/or Synopsys Fusion Compiler / ICC2.
• Strong understanding of Static Timing Analysis (STA) using PrimeTime.
• Experience in Physical Verification using Calibre or equivalent signoff tools.
• Knowledge of IR Drop, EM Analysis, Signal Integrity, Noise Analysis, and Low-Power Design methodologies.
• Hands-on experience in advanced nodes such as 16nm, 7nm, 5nm, or below is preferred.
• Understanding of UPF/CPF and low-power implementation flows.
• Proficiency in TCL, Perl, Python, and Shell scripting for automation and flow enhancement.
• Excellent debugging, problem-solving, communication, and stakeholder management skills.