bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi