Performance Analysis, Linux drivers, workload characterization, systemverilog, CPU GPU benchmark characterization, performance analysis tools, SOC design verification, runtime, mobile SOC performance model development

Asic, Vlsi Design, SoC Verification

Regression Analysis, Cadence Xcelium, Top-Level Verification, wreal Modeling, model validation, Cadence VIVA, Schematic-Level Correlation, Uvm, Coverage-Driven Verification, Analog Circuit Fundamentals, Waveform Debug, SV-RNM, Verification Planning, Cadence ADE Assembler, Simulation Debug, SoC AMS Verification, Digital Design Flow, Mixed-Signal SoC Integration, systemverilog, Verilog-AMS, Cadence SimVision, Cadence Virtuoso, AMS Verification Methodology, Mixed-Signal Verification

scoreboard , test environments , Test Cases, C, Shell, Soc Architecture, Verilog, Agents, Mixed signal designs, Verification testbenches, Debugging RTL and Gate simulations, Verification methodology, Monitors, Regression systems, Testbenches, Sequencers, Industry-standard simulators, Revision control systems, Directed and constrained random verification methodology

Scripting Languages, Sed, Awk, Perl, ARM processor based SoC architecture, ASIC design flow, ASIC verification methodologies, C Assertions coding, multi-core multi-layer APIs, functional coverage, SV-UVM, constraint random test generation, UVM assertion based coverage driven verification, ARM based SOC software framework

System Validation, SOC design, Design Verification

SOC Interfaces, SV/UVM, C/SV

System Verilog, SV UVM based test benches, scripting languages such as Perl, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools