Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, full verification life cycle, revision control systems, AI ML Accelerators, constrained-random verification environments, packet processing, Verification

Perl, Makefile, Ruby, Python, C-DPI, Axi, AMBA, ASIC verification tools, Uvm, AHB, systemverilog

Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, VHDL, Modelsim, Uvm

Shell, Perl, Python, Tcl, Assertions SVA, UVM methodology, Debugging RTL verification issues, Coverage-driven verification, systemverilog, Functional Verification

Debugging, Automated Test Scripts, Documentation, Design Verification, Functional Verification, Test Plan Development

Mac, Pcie, Switches, Ethernet, FPGA verification, RDMA, NICs, SmartNICs, networking architectures, Uvm, systemverilog

analog circuits , Fpga, Logic Design, Verilog, Sta, Scan Insertion, Power product design, Uvm, Synthesis scripts, ATPG generation, Regression frameworks, Synthesis, formal verification, Micro-architecture, ABV, RTL Coding, Timing Constraints, Functional Verification, System-Verilog, Digital Verification, Timing Analysis

Verilog, advanced stimulus generation techniques, Uvm, coverage-driven verification, systemverilog