Verilog, Debugging, Automation Scripting, formal verification, AI-assisted Workflows, Protocol Verification, Property Checking, SVA, systemverilog, Equivalence Checking, Formal Analysis

Scripting, Formal Verification Tools, digital logic, formal verification, Temporal logic assertions

Tcl, Perl, JasperGold, digital design concepts, Questa, VC Formal, systemverilog, debugging complex design bugs, convergence techniques, formal coverage metrics, RTL coding in Verilog, Formal OneSpin, formal verification, formal property specification