RTL Logic design, Jasper VC Formal, writing assertions, formal verification, formal property verification

Shell, Perl, Python, formal property verification, complexity reduction techniques, formal verification technologies, formal testbenches, testplans

Usb, Pcie, Perl, Verilog, Shell scripting, Python, systemverilog, Axi, VHDL, Formal Verification Flow, APB, Cadence JasperGold, AHB

Shell, Python, Perl, complexity reduction techniques, formal verification technologies, high quality testplans, formal testbenches

Tcl, Perl, JasperGold, digital design concepts, Questa, VC Formal, systemverilog, debugging complex design bugs, convergence techniques, formal coverage metrics, RTL coding in Verilog, Formal OneSpin, formal verification, formal property specification

formal verification, Simulation, Data Validation

Python, IBM Formal verification tools, Formal Functional Verification