Formal Verification Engineer
Formal Verification Engineer
ALTEN Calsoft Labs- Posted a month ago
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Job Description
Job Title: Formal Verification Engineer
Location: Bangalore
Experience: 4+Years
Job Type: Full-time
Industry: Semiconductor / ASIC Design / EDA
Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering
Job Description:
We are looking for a highly motivated Formal Verification Engineer to join our Design Verification team. The candidate will be responsible for developing and executing formal verification strategies to ensure functional correctness of complex IP and SoC designs.
Key Responsibilities:
- Define and implement formal verification strategies and plans.
- Develop formal properties and assertions for critical design blocks.
- Apply formal techniques such as property checking, sequential equivalence checking, and formal coverage.
- Analyze formal results, identify unreachable or vacuous properties, and refine models.
- Collaborate closely with RTL designers, DV engineers, and architects.
- Integrate formal into overall verification methodology and sign-off.
- Document and present formal verification methodologies, assumptions, and results.
Required Skills:
- 4+ years of experience in formal verification using industry tools (e.g., JasperGold, VC Formal, Questa Formal, OneSpin).
- Strong knowledge of SystemVerilog Assertions (SVA) and formal property specification.
- Solid understanding of digital design concepts and RTL coding in Verilog/SystemVerilog.
- Familiar with formal coverage metrics and convergence techniques.
- Experience in debugging complex design bugs using formal tools.
- Ability to abstract and model designs or protocols at different levels.
Desirable Skills:
- Familiarity with safety-critical designs (ISO 26262, DO-254) is a plus.
- Knowledge of common protocols: AXI, AHB, PCIe, Ethernet, etc.
- Exposure to sequential equivalence checking and abstraction modeling.
- Understanding of simulation-based verification and integration with formal.
- Proficiency in scripting (Python, Perl, or TCL) for automation.
Interested can Share CV to [Confidential Information]
More Info
Key Skills
digital design concepts
debugging complex design bugs
convergence techniques
JasperGold
Formal OneSpin
VC Formal
formal coverage metrics
RTL coding in Verilog
About Company
Skills:
Data Flow Graphs (DFG), Binary Decision Diagrams (BDD), Verilog, System Verilog, model checking, abstraction modeling, formal verification tools, convergence strategies, equivalence checking, simulation techniques
Skills:
Verilog, VHDL, formal verification, Chisel, JasperGold, VC Formal, Object-oriented Programming, systemverilog, Formal Abstraction Techniques
Skills:
Perl, Verilog, Python, Tcl, SystemVerilog Assertions SVA, VHDL, Synopsys VC Formal, Cadence JasperGold, Property Specification Language PSL, systemverilog
Skills:
C, Perl, Python, Tcl, Formal Verification methods, Formal verification techniques
Skills:
Shell, Perl, Verilog, Automation Scripting, Python, Tcl, SVA, Protocol verification, Formal verification methodologies, systemverilog, RTL analysis, Temporal logic