Formal Verification Engineer

Job Summary

We are hiring a skilled Formal Verification Engineer with strong expertise in Cadence JasperGold for ASIC/SoC verification projects. The ideal candidate should have hands-on experience in Assertion-Based Verification (ABV), property checking, and formal verification methodologies for complex digital designs.

Key Responsibilities

• Perform Formal Verification for IP/Sub-system/SoC level designs using Cadence JasperGold.
• Develop and debug SystemVerilog Assertions (SVA) and formal properties.
• Execute:
• Property Verification
• Connectivity Checks
• X-Propagation Analysis
• Deadlock Detection
• Equivalence Checking
• Understand RTL architecture and create formal verification plans.
• Collaborate with RTL, DV, and Architecture teams for verification closure.
• Analyze counterexamples, debug failures, and identify root causes.
• Improve design quality through assertion coverage and formal methodologies.
• Support verification sign-off activities and documentation.

Required Skills

• 4+ years of experience in ASIC/SoC Verification with strong focus on Formal Verification.
• Hands-on expertise in:
• Cadence JasperGold
• SystemVerilog
• SVA (SystemVerilog Assertions)
• Verilog/VHDL
• Strong understanding of:
• Digital Design Fundamentals
• RTL Design Concepts
• Assertion-Based Verification (ABV)
• Formal Verification Flow
• Experience with industry-standard protocols:
• AXI
• AHB
• APB
• PCIe
• USB
• Scripting knowledge in Python/Perl/Shell scripting.
• Good debugging and analytical skills.

Preferred Qualifications

• Bachelor's/Master's degree in Electronics/ECE/VLSI or related field.
• Exposure to UVM-based verification is an added advantage.
• Knowledge of low-power verification concepts is preferred.
• Experience in networking/storage/datacenter SoC verification is a plus.

Nice to Have

• Exposure to CDC/RDC verification.
• Experience in automation and regression environments.
• Knowledge of FPGA/Emulation platforms.

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