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Exp Level: 4.5+ years to 10 years
JD:
• Experience in formal verification of customer RTL/Logic design blocks
• Experience in any of formal tools – Jasper, VC Formal
• Formal property verification
• Experience in writing assertions
Job ID: 148913833
Skills:
Verilog, Python, Formal Functional Verification, HDLs, VHDL, Processor core u-arch, SV, IBM Formal verification tools
Skills:
Shell, Perl, Python, formal property verification, complexity reduction techniques, formal verification technologies, formal testbenches, testplans
Skills:
Usb, Pcie, Perl, Verilog, Shell scripting, Python, systemverilog, Axi, VHDL, Formal Verification Flow, APB, Cadence JasperGold, AHB
Skills:
Cadence LEC, formal verification, Physical Design, Conformal ECO generation
Skills:
Cadence LEC, formal verification, Physical Design, Conformal ECO generation, RTL
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