Python, Systemc, MDV, simulation scripts, hybrid testbenches, regression systems, verification execution, Uvm, systemverilog, testbenches, CDV, coverage models

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

Fpga, Python, Perl, formal verification methods, object-oriented design, Uvm, AMBA bus protocols, RTL, systemverilog, low power verification methods, transaction level modeling, emulation platforms, test plan development, Baremetal processor environments

C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog

DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog

bandwidth management , Microprocessor Cores, interconnects, standard IP components, systemverilog, hierarchical memory subsystems, Specman E, constrained-random verification, Verification, IP subsystem SoCs, packet processing, congestion control, Debug

Cpu, Ethernet, Pcie, Debugging, DDR, Uvm, Assertions, SoC Integration, SV, Coverage Closure, Complex Verification Flows, RISC-V, formal verification, IP Sub-System SoC DV Testbench Development

Verilog, Scripting Languages, Verification Tools, VHDL, Uvm, formal verification, Simulators