Python Scripting, Git, ASIC design flow, RTL design in Verilog, Version control systems such as Perforce, ICManage, Modern SOC tools including Spyglass, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools, Cadence Conformal, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, Questa CDC, VCS simulation

Shell, Tcl, Perl, DMA, digital design fundamentals, control data path logic, protocol bridges, low-power design flows, systemverilog, power performance and area optimization techniques, lint CDC RDC synthesis STA constraints, RTL design using Verilog, memory-mapped peripherals, micro-architecture definition, Dft, bus fabrics, debugging skills for simulation synthesis and integration issues

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram

Shell scripting, Tcp Ip, Ethernet, Perl, Pcie, Design for Test methodologies, networking IP solutions, NVMe based Storage IP, Verilog RTL design, RDMA IPs, Silicon IP development process methodologies, VCS simulation tool, DMAs

RDC, RTL coding expertise in Verilog, SpyGlass Lint, micro-architecture development, systemverilog, FSM design, Pipelining techniques, ASIC SoC design flow, Datapath architecture, cdc, Clock and Reset domain crossings

Perl, Verilog, Tcl, Python, VHDL, AXI Protocols, Ethernet protocol, Ethernet IPs, Rtl Design

Tcl, Python Scripting, Perl, PrimeTime or equivalent tools, ASIC design flow, Low power digital design and analysis, ASIC design in sub-20nm technology nodes, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog

Perl, ASIC, Digital Design, Sta, Circuit timing, Rtl Design