Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms

Verilog, systemverilog, DDR memory controller calibration, Rtl Design, Logic analyzers, Calibration algorithms

Python Scripting, RTL design in Verilog SystemVerilog, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, PrimeTime or equivalent tools, C embedded experience, Circuit timing STA

Debugging, System Verilog, Sta, Synthesis, Wi-Fi, FPGA RTL design, Uvm, DSP fundamentals, Wireless Communication, 5G, VHDL, high-speed packet processing, AMD Zynq RFSoC, FPGA design flow, Timing Closure, 5G LTE, Altera Agilex

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes

Verilog, Uvm, Synopsys VCS, Cadence Incisive, VHDL, RTL design methodologies, Modelsim

Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies

RDC, Pipelining techniques, Datapath architecture, cdc, SpyGlass Lint, RTL coding expertise in Verilog, Clock and Reset domain crossings, micro-architecture development, ASIC SoC design flow, systemverilog, FSM design