routing, floor-planning, physical design flows, digital VLSI concepts, Tempus, Cadence Innovus, Voltus, Logic Synthesis, Rtl Design, EDA Tools, Timing Closure, Placement

rc extraction , Ecos, Perl, Tcl, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing analysis and verification, Synthesis, PNR, Physical Design, DRC, Antenna, Cross talk, formal verification, IR-EM checks, Place And Route, Timing Analysis

Voltus, Backend Signoff flows, Cell EM, LVS, SigEM, Power Grid planning, pegasus, Cadence Tools, Innovus, PERC, EMIR, Tempus, Esd, Signal and Power bump planning, DRC

synopsys primetime , Scripting, Shell, Perl, Python, Tcl, Siemens Calibre, IR drop, Fusion Compiler, Cadence Tools, Power Reliability, ICC2, Tempus, LVS, Innovus, Physical Verification, Timing Analysis, ERC, Physical Design Tools, Synopsys Design Compiler, Genus, DRC, EM noise analysis

Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm

fusion compiler, physical design solutions, Design Tools

rc extraction , Ecos, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing Closure, Dft, Synthesis, PNR, DRC, Physical design flow, Cross talk, Verification Tools, formal verification, IR-EM checks, Place And Route, Timing Analysis